A lithographic projection apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, a mask may contain a circuit pattern corresponding to at least a part of an individual layer of the IC (“design layout”), and this circuit pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the circuit pattern on the mask. In general, a single substrate contains a plurality of adjacent target portions to which the circuit pattern is transferred successively by the lithographic projection apparatus, one target portion at a time. In one type of lithographic projection apparatuses, the circuit pattern on the entire mask is transferred onto one target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, a projection beam scans over the mask in a given reference direction (the “scanning” direction) while synchronously moving the substrate parallel or anti-parallel to this reference direction. Different portions of the circuit pattern on the mask are transferred to one target portion progressively. Since, in general, the lithographic projection apparatus will have a magnification factor M (generally <1), the speed F at which the substrate is moved will be a factor M times that at which the projection beam scans the mask. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
A lithography process in which features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus are printed, is commonly known as low-k1 lithography, according to the resolution formula CD=k1×λ/NA, where λ is the wavelength of radiation employed (currently in most cases 248 nm or 193 nm), NA is the numerical aperture of projection optics in the lithographic projection apparatus, CD is the “critical dimension”—generally the smallest feature size printed—and k1 is an empirical resolution factor. In general, the smaller k1 the more difficult it becomes to reproduce a pattern on the wafer that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the lithographic projection apparatus as well as to the design layout. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting masks, optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) in the design layout, or other methods generally defined as “resolution enhancement techniques” (RET).
As one example, OPC addresses the fact that the final size and placement of an image of the design layout projected on the substrate will not be identical to, or simply depend only on the size and placement of the design layout on the mask. It is noted that the terms “mask” and “reticle” are utilized interchangeably herein. Furthermore, masks and reticles can be broadly termed “patterning devices.” Also, person skilled in the art will recognize that, especially in the context of lithography simulation/optimization, the term “mask” and “design layout” can be used interchangeably, as in lithography simulation/optimization, a physical mask is not necessarily used but a design layout can be used to represent a physical mask. For the small feature sizes and high feature densities present on some design layout, the position of a particular edge of a given feature will be influenced to a certain extent by the presence or absence of other adjacent features. These proximity effects arise from minute amounts of light coupled from one feature to another and/or non-geometrical optical effects such as diffraction and interference. Similarly, proximity effects may arise from diffusion and other chemical effects during post-exposure bake (PEB), resist development, and etching that generally follow lithography.
In order to ensure that the projected image of the design layout is in accordance with requirements of a given target circuit design, proximity effects need to be predicted and compensated for, using sophisticated numerical models, corrections or pre-distortions of the design layout. The article “Full-Chip Lithography Simulation and Design Analysis—How OPC Is Changing IC Design”, C. Spence, Proc. SPIE, Vol. 5751, pp 1-14 (2005) provides an overview of current “model-based” optical proximity correction processes. In a typical high-end design almost every feature of the design layout requires some modification in order to achieve high fidelity of the projected image to the target design. These modifications may include shifting or biasing of edge positions or line widths as well as application of “assist” features that are intended to assist projection of other features. The assist features may include SRAF (Sub Resolution Assist Features) or PRAF (Printable Resolution Assist Features).
Application of model-based OPC to a target design requires good process models and considerable computational resources, given the many millions of features typically present in a chip design. However, applying OPC is generally not an “exact science,” but an empirical, iterative process that does not always compensate for all possible proximity effect. Therefore, effect of OPC, e.g., design layouts after application of OPC and any other RET, need to be verified by design inspection, i.e. intensive full-chip simulation using calibrated numerical process models, in order to minimize the possibility of design flaws being built into the manufacturing of a mask. This is driven by the enormous cost of making high-end masks, which run in the multi-million dollar range, as well as by the impact on turn-around time by reworking or repairing actual masks once they have been manufactured.
Both OPC and full-chip RET verification may be based on numerical modeling systems and methods as described, for example in, U.S. patent application Ser. No. 10/815,573 and an article titled “Optimized Hardware and Software For Fast, Full Chip Simulation”, by Y. Cao et al., Proc. SPIE, Vol. 5754, 405 (2005).
In addition to optimization to design layouts or masks (e.g., OPC), the illumination source can also optimized, either jointly with mask optimization or separately, in an effort to improve the overall lithography fidelity. Since the 1990s, many off-axis illumination sources, such as annular, quadrupole, and dipole, have been introduced, and have provided more freedom for OPC design, thereby improving the imaging results. As is known, off-axis illumination is a proven way to resolve fine structures (i.e., target features) contained in the mask. However, when compared to a traditional illumination source, an off-axis illumination source usually provides less light intensity for the aerial image (AI). Thus, it becomes desirable to attempt to optimize the illumination source to achieve the optimal balance between finer resolution and reduced light intensity. The terms “illumination source” and “source” are used interchangeably in this document.
Numerous illumination source optimization approaches can be found, for example, in an article by Rosenbluth et al., titled “Optimum Mask and Source Patterns to Print A Given Shape,” Journal of Microlithography, Microfabrication, Microsystems 1(1), pp. 13-20, (2002). The source is partitioned into several regions, each of which corresponds to a certain region of the pupil spectrum. Then, the source distribution is assumed to be uniform in each source region and the brightness of each region is optimized for process window. However, such an assumption that the source distribution is uniform in each source region is not always valid, and as a result the effectiveness of this approach suffers. In another example set forth in an article by Granik, titled “Source Optimization for Image Fidelity and Throughput,” Journal of Microlithography, Microfabrication, Microsystems 3(4), pp. 509-522, (2004), several existing source optimization approaches are overviewed and a method based on illuminator pixels is proposed that converts the source optimization problem into a series of non-negative least square optimizations. Though these methods have demonstrated some successes, they typically require multiple complicated iterations to converge. In addition, it may be difficult to determine the appropriate/optimal values for some extra parameters, such as γ in Granik's method, which dictates the trade-off between optimizing the source for wafer image fidelity and the smoothness requirement of the source.
During exposures, elements in the lithographic projection apparatus may deform. The deformations may be caused by many factors, such as radiation absorption, temperature change, mechanical movement, chemical reaction, etc. The deformations can contribute adversely to accurate projection of the design layout onto the substrate. Mechanisms that account or compensate for these deformations may be used to reduce or eliminate the adverse contribution. The deformations in the elements can be interdependent, which makes efforts to account or compensate for the deformations difficult.
In one example, the projection system may absorb radiation, heat-up and therefore introduce aberrations into the projection system, resulting in reduced image quality at substrate level. These effects are particularly acute when using illumination modes, such as dipole and quadrupole illuminations, and/or deep ultraviolet radiation (DUV), e.g. at 198, 157 or 126 nm, since the choice of materials from which lenses useable with these wavelengths can be made is generally limited and even the best materials have significant coefficients of absorption at those wavelengths. The problem particularly affects projection systems formed by refractive lens elements and is therefore often referred to as lens heating. Even with cooling systems that maintain the projection system at a constant temperature, sufficient local temperature variations can occur which can cause noticeable loss of imaging quality.
Therefore, many projection systems in lithographic projection apparatus are provided with one or more actuated adjustable elements whose shape, position and/or orientation in one or more degrees of freedom can be adjusted during or between exposures to compensate for lens heating effects. A computer model predicts the lens heating effects that are expected and calculates appropriate corrections to be effected by the adjustable elements. Computer models may be used to calculate the lens heating effects in terms of Zernike polynomials describing the aberrations in the pupil plane of the projection system and applied corrections via control “knobs” on the projection system that adjust one or more adjustable elements to give a correction corresponding to the relevant Zernike polynomial. Other attempts to deal with the problem of non-uniform lens heating include the provision of additional light sources, e.g. infra-red, to heat the “cold” parts, i.e. those not traversed by the intense parts of the projection beam, of elements of the projection system, see U.S. Pat. No. 6,504,597 and JP-A-08-221261. The former reference addresses non-uniform heating caused by a slit-shaped illumination field and the latter reference addresses non-uniform heating caused by zonal or modified illumination. The provision of such additional light sources and guides to conduct the additional heating radiation to the correct places may increase the complexity of the apparatus and the increased heat load in the projection system necessitates the provision of a cooling system of higher capacity.
Two approaches are conventionally pursued to account for lens heating effects.
In a first approach, which is used by lithography users to control lens heating issues in a production environment, the lens heating behavior is experimentally measured during a production lot. This empirically-generated lens heating data can then be used to calculate corrections which are applied to the projection system during a lot exposure. A series of lens actuators are available in the lithographic apparatus and can be used to move active elements, as the lens heats, that reduce the aberration signature through the production lot.
However, because the first approach is entirely driven by experiments, this requires that the lithographic apparatus be used during a significant amount of time to collect the lens heating data which are specific to the process under study. Moreover, in some circumstances, the lithographic apparatus does not have the dynamic range necessary to correct for the entire range of aberrations observed during production. Thus, limitations of the lithographic apparatus should also be considered for this empirically driven approach.
In a second approach, the expected lens heating signature is modeled through a simulation program (e.g. Tachyon Lens Heating Module). The simulations of the expected lens heating signature allow users to examine the predicted behavior of a proposed mask layout or pattern and identify the features that are most sensitive to lens heating-induced aberrations. Based on the predicted lens heating impact, the design can be iteratively modified to mitigate the most severe lens heating-induced aberrations. While time consuming and iterative in nature, this second approach is faster than the first approach which is driven entirely by lens heating experiments and lithographic apparatus controls. An example embodying the second approach can be found is commonly assigned U.S. Publication No. US-2013-0212543-A1, which is incorporated by reference in its entirety.